1. Field of the Invention
The present invention relates to a single-error detecting and correcting system which can detect and corrects a single parity error in control data read out from a control data memory.
2. Description of the Related Art
As the scale and capabilities of computers expand, failures occurring in the computers become more important. Thus, various measures are taken against such failures. For example, as measures against errors in data read from a control data memory, a parity check and a SEC-DED (Single Error Correcting-Double Error Detecting) system have conventionally been used.
With a longitudinal or lateral parity checking system, the number of check bits and the amount of hardware required may advantageously be small. However, though an error can be detected, the error cannot be corrected. With the SEC-DED system, on the other hand, a single error can be corrected, but the number of check bits and the amount of hardware required increase. Increasing the number of check bits to, for example, one byte for a data part of eight bytes results in costly error detecting and correcting system which requires an expensive high-speed operational memory.